In a phase locked loop (PLL) the output signal is phase and frequency locked to an input reference signal. A PLL with a frequency divider inserted in the feedback loop can be used to make an Integer-N frequency synthesizer. In that case the signal at the phase detector negative input is phase and frequency locked to the reference. The output frequency and phase is N times the reference frequency and phase. Output frequencies can be synthesized in steps of the reference frequency by programming the value of N. There are exactly N periods of the output for every period of the reference and therefore one rising edge of the output in every N is in phase with each rising edge of the reference. For any given value of N the phase of the output relative to the reference is fixed and is the same each time the synthesiser is switched back to that frequency channel. In a fractional-N synthesiser, the divider in the feedback path has an integer and fractional part and the output frequency step resolution is a fraction of the reference frequency, as shown in equation (1):
                              f          OUT                =                              (                          N              +                              F                M                                      )                    ×                      f            REF                                              (        1        )            
The fractional part is generated using a digital interpolator. This outputs a sequence of integer values with an average value given by F/M where F is the input fraction and M is the modulus. The modulus M can be programmable also or it may be fixed for a given implementation.
The interpolator could be for instance, a single accumulator with the overflow bit as output or it could be a higher order sigma-delta modulator. There are numerous prior art examples of both architectures.
Fractional-N synthesizers have a number of advantages which make them desirable. Their output steps are in fractions of the reference frequency. This allows the use of larger input reference frequencies which in turn allows N to be smaller. This is a major advantage because phase noise gain from input to output is a function of N2 or 20 Log N in dB's so the noise can be much reduced by even a small reduction in N. Also the availability of a larger reference frequency allows a wider loop bandwidth which in turn allows a shorter settling time each time the synthesizer is switched from one frequency channel to another.
By rewriting equation (1) as follows:
                              f          OUT                =                              (                                          M                ⁢                                                                  ⁢                N                            +              F                        )                    ×                                    f              REF                        M                                              (        2        )            it is clear that the output will only be in phase with one out of every M edges of the input reference. This highlights a major disadvantage of fractional-N synthesizers in that the output phase can have any one of M possible values with respect to the input reference phase, where M is the fractional modulus. Which one of the M edges of the reference this will be may be different each time the channel is synthesized depending on the particular state of the interpolator when the new N and F values, which specify the channel to be synthesized, are loaded. In some applications this doesn't matter but when it is required that a particular output frequency signal has consistently the same phase relationship with a reference then this is a problem with a fractional-N synthesizer.
This problem has been addressed in U.S. Pat. No. 6,556,086. In that approach synchronization pulses are provided every K cycles with respect to fref where K is a multiple of M. A disadvantage of this implementation is that if M is very large then the time interval between synchronization pulses will be long. For example, if M is chosen to provide 1 Hz output resolution then the time interval between synchronization pulses will be 1 second. This is a problem in applications that require a shorter settling time to final phase. Another disadvantage is that it requires divide-by-K synchronization counter to be continuously clocked by the reference. As well as in increased power consumption, the switching noise due to this activity may degrade the synthesizers phase noise performance or cause spurious sidebands at offsets of +/−fref/K around the synthesizer output carrier frequency. In some applications, where a plurality of fractional-N synthesizers are driven from a common reference frequency, it is only required that the outputs of the synthesizers have a consistent phase relationship with each other, not necessarily with the input reference. This reduced requirement allows an alternative structure that avoids the listed disadvantages of the implementation of U.S. Pat. No. 6,556,086.